The present invention relates generally to the field of semiconductor device manufacturing, and more particularly to a method of fabricating circuits comprised of both polycrystalline and amorphous silicon devices in close proximity to one another.
Amorphous silicon (a-Si) is a material commonly employed for example in largearea electronic devices such image sensors, displays, etc. Active matrix liquid crystal displays (AMLCDs), for instance, may be comprised of 7 million or more pixels formed on a sheet of glass 25 cm by 20 cm or larger, where each pixel includes one or more transistors formed in part of a-Si. A two dimensional (2-d) imager with a similar pixel count may be 46.5 cm by 36 cm, for example. In addition to the pixel transistor(s), AMLCDs, image sensors, and the like often require related circuitry such as drivers, decoders, etc. It is desirable to integrate this related circuitry onto the glass substrate to reduce size, cost, etc. Most commonly, this related circuitry is located at the periphery of the pixel array on the substrate.
It is well recognized that devices fabricated from a-Si are relatively slow-due to the poor carrier mobility in a-Si. While adequately fast to serve as pixel thin film transistors (TFTs), a-Si transistors are considered too slow to provide adequate performance of the related circuitry. One technique employed to address this shortfall of a-Si devices has been to use polycrystalline silicon (poly-Si) devices for the related circuitry. Poly-Si TFTs, for example, provide a 20 to 100-fold improvement in carrier mobility over a-Si TFTs, thus proportionally increasing device speed. Poly-Si devices may be formed on the same substrate as a-Si devices, the processing steps being compatible for the two different materials.
However, it is also well recognized that a-Si devices provide some advantages over poly-Si devices. Poly-Si TFTs have a higher leakage current, for example more than two orders of magnitude, than similar a-Si devices, which is undesirable for applications such as 2-d imaging arrays. Thus, it is preferable to exploit the desirable to properties of both a-Si and poly-Si devices in a single array. A structure comprised of both a-Si and poly-Si devices on a shared substrate is referred to herein as a hybrid structure.
One method disclosed in the art for forming poly-Si TFTs on a shared substrate with a-Si TFTs is referred to as laser crystallization. There are numerous embodiments of laser crystallization. According to one such embodiment, a SiO2 gate insulation film is grown on a highly doped single crystal silicon substrate which serves as a gate electrode. An a-Si film is next deposited by chemical vapor deposition (CVD) onto the SiO2 film. The a-Si film is then crystallized by excimer laser annealing, and hydrogenated by further annealing in the presence of hydrogen. Aluminum patterned over the top of this structure provides the electrical contacts. A method of this type is taught by Shimizu et al. in xe2x80x9cOn-Chip Bottom-Gate Polysilicon and Amorphous Silicon Thin-Film Transistors Using Excimer Laser Annealing,xe2x80x9d Japanese J. of Appl. Phys., vol. 29, no. 10 pp. 1775 et seq. (October 1990). A similar method taught by U.S. Pat. No. 5,366,926, which is incorporated herein by reference, employs a pulsed laser to crystallize a-Si material to form a poly-Si channel for a TFT.
Known techniques for laser crystallization have several disadvantages. For example, it has been commonly assumed that poly-Si devices would be formed on the substrate periphery, thus relatively far away from a-Si devices. In such case, limited or no masking is required. And if a mask is needed, a shadow mask protecting the a-Si device from the laser during the crystallization process is adequate. However, recent pixel designs for high performance arrays include poly-Si and a-Si devices in very close proximity to one another, for example on the order of 5 xcexcm or less from edge to adjacent edge. This is not possible from current process, which are designed for separations between poly-Si and a-Si devices on the order of 3 mm. New techniques and structures are required to provide this close spacing between devices.
The present invention is a novel process and structure which overcomes the disadvantages referred to above. In particular, we have discovered a novel process for the formation of a device, such as a TFT, having a poly-Si conductive region formed from what was originally an a-Si layer. Furthermore, the process and related structure is ideally suited to the formation of a-Si and poly-Si devices on a shared substrate at a spacing of between 2 and 50 xcexcm. Minimal additional processing is required over existing techniques, and all additional steps and materials are compatible with existing manufacturing processes.
An exemplary process according to the present invention begins with the formation of metal gate lines on a substrate such as glass. A dielectric layer is deposited over the gate metal and substrate, and an a-Si layer is deposited over the dielectric layer. An oxide insulation layer is deposited over the a-Si layer. Finally, an a-Si layer, referred to herein as a compensation or absorption layer, is applied over the oxide layer. The thickness of this a-Si compensation layer is selected to provide to improved absorption of the ultra violet (UV) radiation used in a back-side lithography process employed to form a conductive region, such as a channel, of the device being fabricated. The back-side lithography is then performed, and a doped or intrinsic silicon layer is applied over the structure. If the silicon is intrinsic, doping is then performed to obtain the desired structure. Gaps and contact metal are then formed to complete the device.
In addition, should it be desired to form the poly-Si device in close proximity to the a-Si device, the following additional steps may be employed. First, a nitride layer such as silicon nitride is applied over the region in which the device which shall remain a-Si is to be formed. A layer of titanium tungsten (TiW) alloy is then also formed over the region in which the device which shall remain a-Si is to be formed. This TiW layer, together with the nitride layer, serves as an optical mask to protect the region in which the device which shall remain a-Si is to be formed during laser crystallization. In substantial part, it is the effectiveness of this mask, and the ability to define its location photolithographically that allows for the formation of poly-Si and a-Si devices at a spacing as small as between 2 and 50 xcexcm.
Following the laser crystallization, the TiW layer is removed. The structure is then rehydrogenated to compensate for the dehydrogenation during the laser crystallization. The nitride layer over the region which is to become the a-Si device serves to protect the a-Si layer from the hydrogenation process. Processing then continues as previously described.
Thus, the present invention and its various embodiments provide numerous advantages including, but not limited to significant reduction in inter-device spacing, simple integration into existing processes, etc., as described in further detail herein.